The Turn of Moore’s Law from Space to Time by Liming Xiu

Author:Liming Xiu
Language: eng
Format: epub
ISBN: 9789811690655
Publisher: Springer Nature Singapore

Gestalt Switch:

The resolution of the two long-lasting problems (arbitrary frequency generation and instantaneous frequency switching) enables new treatment on old problems. In this section, the problem of chirp signal generation is simplified by using a newer and more powerful tool.

6.6 Frequency Lock on Time-Average-Frequency: All Digital TAF-FLL

A frequency-locked loop (FLL) is an electronic control system that generates a signal whose frequency is locked to the frequency of a “reference” signal. This circuit compares the frequency of a controlled oscillator to the reference, automatically raising or lowering the frequency of the oscillator until its frequency is matched to that of the reference (or multiple of the reference). It is an example of control system using negative feedback. FLLs are used in radio, telecommunications, computers and etc., to generate stable frequencies, or to recover a signal from a noisy communication channel. It is also used in many other electronic applications such as frequency measurement, synchronization to power grid, oscillator frequency stabilization, FM spectroscopy, transceiver RF synchronization and etc. A phase-lock, or phase-locked loop (PLL), is one step further than frequency-lock. PLL is a control system that generates an output signal, in addition to frequency match, whose phase is also related to the phase of the input signal.

Both PLL and FLL are well studied circuit architectures. Traditionally, they are built mostly from analog components. The most popular monolithic PLL architecture in IC design is the third-order type II charge pump PLL. Nowadays, with the advance of digital process, digital processing of digitized analog signals becomes a popular approach of designing such frequency control loops. This new technique of processing digitized analog signal results in all-digital PLL (ADPLL) wherein the analog signal processing in loop design is replaced by digital signal processing. References (Staszewski et al. 2005; Wu et al. 2017) present the first and a recent example of all-digital PLL (ADPLL). ADPLL is achieved by innovations in the frequency/phase detection (PFD) and oscillator control (VCO). The traditional PFD is replaced by Time-to-Digital Converter (TDC) so that the error signal is expressed in a digital fashion. In such so-called ADPLL, the oscillator is typically made of on-chip inductor and capacitor. Its frequency tuning is accomplished by tuning on and off individual small capacitors in an array. This action takes place in digital domain. Thus, it is called digitally controlled oscillator (DCO). The use of TDC and DCO leads to the possibility of using digital filter in the loop design.

In some recent cases, the term ADPLL also has been used to refer to those architectures where CMOS gate-delay structures are employed for generating oscillation frequency (inductor-less). The oscillator is also digitally controlled (DCO) (Chung et al. 2016; Ho and Yao 2016). For all those ADPLLs, the all-digital nature of the loop filter enables the ADPLL to enjoy many implementation advantages, such as improved noise immunity from circuit nonidealities, compatibility with digital deep submicron CMOS process, simplified testing and calibration, and ease of integration with digital baseband circuitries. Further, the digital nature of the loop structure

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